The present invention relates generally to integrated circuits and in particular the present invention relates to column decode circuits in memory arrays.
Memory devices are typically provided as internal storage areas in the computer. The term memory identifies data storage that comes in the form of integrated circuit chips. There are several different types of memory used in modern electronics, one common type is RAM (random-access memory). RAM is characteristically found in use as main memory in a computer environment. RAM refers to read and write memory; that is, you can both write data into RAM and read data from RAM. This is in contrast to ROM, which permits you only to read data. Most RAM is volatile, which means that it requires a steady flow of electricity to maintain its contents. As soon as the power is turned off, whatever data was in RAM is lost.
Computers almost always contain a small amount of read-only memory (ROM) that holds instructions for starting up the computer. Unlike RAM, ROM cannot be written to. An EEPROM (electrically erasable programmable read-only memory) is a special type non-volatile ROM that can be erased by exposing it to an electrical charge. EEPROM comprise a large number of memory cells having electrically isolated gates (floating gates). Data is stored in the memory cells in the form of charge on the floating gates. Charge is transported to or removed from the floating gates by specialized programming and erase operations, respectively.
Yet another type of non-volatile memory is a Flash memory. A Flash memory is a type of EEPROM that can be erased and reprogrammed in blocks instead of one byte at a time. A typical Flash memory comprises a memory array, which includes a large number of memory cells. Each of the memory cells includes a floating gate field-effect transistor capable of holding a charge. The data in a cell is determined by the presence or absence of the charge in the floating gate. The cells are usually grouped into sections called xe2x80x9cerase blocksxe2x80x9d. Each of the cells within an erase block can be electrically programmed in a random basis by charging the floating gate. The charge can be removed from the floating gate by a block erase operation, wherein all floating gate memory cells in the erase block are erased in a single operation. For ease of access and management the erase blocks of a non-volatile memory device are typically arranged in xe2x80x9cbanksxe2x80x9d or segments.
Many modern PCs have their BIOS stored on a flash memory chip so that it can easily be updated if necessary. Such a BIOS is sometimes called a Flash BIOS. Flash memory is also popular in modems because it enables the modern manufacturer to support new protocols as they become standardized.
Both RAM and ROM random access memory devices have memory cells that are typically arranged in an array of rows and columns. During operation, a row (page) is accessed and then memory cells can be randomly accessed on the page by providing column addresses. This access mode is referred to as page mode access. To read or write to multiple column locations on a page requires the external application of multiple column addresses. To increase access time, a burst mode access has been implemented. The burst mode uses an internal column address counter circuit to generate additional column addresses. The address counter begins at an externally provided address and advances in response to an external clock signal or a column address strobe signal.
A synchronous DRAM (SDRAM) is a type of DRAM that can run at much higher clock speeds than conventional DRAM memory. SDRAM synchronizes itself with a CPU""s bus and is capable of running at 100 MHZ or 133 MHZ, about three times faster than conventional FPM (Fast Page Mode) RAM, and about twice as fast EDO (Extended Data Output) DRAM and BEDO (Burst Extended Data Output) DRAM. A modern extended form of SDRAM, that can transfer a data value on the rising and falling edge of the clock signal, is called the double data rate SDRAM (DDR SDRAM, or simply, DDR). SDRAM""s can be accessed quickly, but are volatile. Many computer systems are designed to operate using SDRAM, but would benefit from non-volatile memory. A synchronous Flash memory has been designed that allows for a non-volatile memory device with an SDRAM interface. Although knowledge of the function and internal structure of a synchronous Flash memory is not essential to understanding the present invention, a detailed discussion is included in U.S. patent application Ser. No. 09/627,682 filed Jul. 28, 2000 and titled, xe2x80x9cSynchronous Flash Memory,xe2x80x9d which is commonly assigned and incorporated by reference.
FIG. 1 shows a simplified diagram of a system 128 incorporating a Flash memory 100 of the prior art coupled to a processing device or controller 102. The Flash memory 100 has an address interface 104, a control interface 106, and a data interface 108 that are each coupled to the processing device 102 to allow memory read and write accesses. Internally to the Flash memory device a control state machine 110 directs internal operation of the Flash memory device; managing the Flash memory array 112 and updating RAM control registers and non-volatile erase block management registers 114. The RAM control registers and tables 114 are utilized by the control state machine 110 during operation of the Flash memory 100. The Flash memory array 112 contains a sequence of memory banks or segments 116. Each bank 116 is organized logically into a series of erase blocks (not shown). Memory access addresses are received on the address interface 104 of the Flash memory 100 and divided into a row and column address portions. On a read access the row address is latched and decoded by row decode circuit 120, which selects and activates a row page (not shown) of memory cells across a selected memory bank. The bit values encoded in the output of the selected row of memory cells are coupled from a local bitline (not shown) to a global bitline (not shown) and detected by sense amplifiers 122 associated with the memory bank. The column address of the access is latched and decoded by the column decode circuit 124. The output of the column decode circuit selects the desired column data from the sense amplifier outputs and coupled to the data buffer 126 for transfer from the memory device through the data interface 108. On a write access the row decode circuit 120 selects the row page and column decode circuit selects write sense amplifiers 122. Data values to be written are coupled from the data buffer 126 to the write sense amplifiers 122 selected by the column decode circuit 124 and written to the selected floating gate memory cells (not shown) of the memory array 112. The written cells are then reselected by the row and column decode circuits 120, 124 and sense amplifiers 122 so that they can be read to verify that the correct values have been programmed into the selected memory cells.
Sense amplifiers of modern memory devices are typically incorporated internal to the memory arrays. Many modern memory architectures with dense memory arrays save on scarce circuit and routing resources by not fully decoding the column address before it is routed into the array proper, minimizing the number of column select lines and circuit resources they utilize routing through the array. Once the partially decoded column select lines are routed to the sense amplifiers in the interior of the memory array, the remainder of the column address is decoded to select the appropriate read and write sense amplifiers. Typically this decoding is accomplished by a series coupled sequence of pass transistors which selectively enable to pass the output of the desired sense amplifiers.
This partial decoding approach avoids the circuit and routing resource expense of a fully decoded column address approach. However, the partial decoding approach increases the number of xe2x80x9clogic levelsxe2x80x9d of the resulting column decoder circuit, increasing complexity and overall circuit size. The additional logic levels of the partial decoding column decode circuit add additional circuit delay to the decoding of the asserted column address. Partial decoding also has the effect of increasing the resistance seen by the sense amplifiers by inserting multiple pass transistors into the input path of write sense amplifiers or output path of read sense amplifiers. With the faster access speeds of modern memory devices the additional delays of the partial column decoder circuit and pass transistors are more of an issue for modern memory devices.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for an improved memory column address decoding scheme.
The above-mentioned problems memory column address decoding in memory devices are addressed by the present invention and will be understood by reading and studying the following specification.
In one embodiment, a column decoder circuit comprises a memory array with a plurality of sense amplifiers, a decoder circuit adapted to receive and fully decode a column address, a plurality of column select lines coupled to the decoder circuit, wherein the column select lines are routed across the memory array and selectively couple the plurality of sense amplifiers to an array output bus by activating a single pass transistor coupled to each sense amplifier.
In another embodiment, a Flash memory Y-Mux circuit comprises a memory array with a plurality of sense amplifiers, an address interface coupled to an address decoder, and a plurality of decode lines coupled to the address decoder, wherein a single pass transistor is coupled to each sense amplifier and each decode line is coupled to at least one pass transistor.
In a yet another embodiment, a Flash memory device comprises a memory array containing a plurality of floating gate memory cells, an address interface coupled to a row address decoder and a column address decoder, and a plurality of column decode lines coupled to the column address decoder, wherein the column decode circuit is adapted to fully decode a column address and wherein each column decode line is coupled to a single pass transistor.
In a further embodiment, a non-volatile memory array comprises a plurality of sense amplifiers, an address decoder, and a plurality of decode lines coupled to the address decoder, wherein a single pass transistor is coupled to each sense amplifier and wherein each decode line is coupled to at least one pass transistor.
In yet a further embodiment, a Flash memory device comprises a memory array with a plurality of memory banks, wherein each memory bank has a plurality of read sense amplifiers and a plurality of write sense amplifiers, a data input bus coupled to a data buffer, wherein each write sense amplifier is coupled to the data input bus with a single pass transistor, a data output bus coupled to the data buffer, wherein each read sense amplifier is coupled to the data output bus with a single pass transistor, an address interface coupled to a row address decoder and a column address decoder, wherein the column address decoder is a single logic level and is adapted to fully decode the column address, and a plurality of column select lines coupled to the column address decoder, wherein each column select line is coupled to at least one pass transistor.
In another embodiment, a system comprises a processor, and a Flash memory device coupled to the processor. The Flash memory device includes a memory array, a memory array containing a plurality of floating gate memory cells, an address interface coupled to a row address decoder and a column address decoder, and a plurality of column decode lines coupled to the column address decoder, wherein the column decode circuit is adapted to fully decode a column address and wherein each column decode line is coupled to a single pass transistor.
In yet another embodiment, a method of operating a Flash memory device comprises receiving a memory access containing a memory address at a memory device, decoding the memory address with an address decoder, and accessing a memory array of the Flash memory device by activating at least one decode select line of a plurality of decode select lines, wherein each of the at least one decode select lines selectively couples at least one sense amplifier to a data bus with a pass transistor.
In a further embodiment, a method of making a Flash memory device comprises forming a memory array with a plurality of sense amplifiers that each couple to a data bus with a single pass transistor, forming an address interface, forming an address decode circuit coupled to the address interface, and forming a plurality of decode select lines each coupled to the address decoder and at least one of the pass transistors.
In yet a further embodiment, a method of operating a Flash memory device comprises receiving a memory access containing a column address at a memory device, fully decoding the column address with a column address decoder, accessing a memory array of the Flash memory device by activating at least one decode select line of a plurality of decode select lines, wherein each of the at least one decode select lines is routed through a metal process layer over the memory array and selectively couples at least one sense amplifier to a data bus with a Y-MUX.
In another embodiment, a Flash memory device comprises a memory array containing a plurality of floating gate memory cells, a plurality of bit lines, wherein each bit line is coupled to a sense amplifier and to a plurality of outputs of the plurality of floating gate memory cells, an address interface coupled to a row address decoder and a column address decoder, a plurality of column decode lines coupled to the column address decoder, wherein the column address decoder is adapted to fully decode a column address and wherein each column decode line is routed through a metal process layer of the memory array, and a Y-MUX, wherein each Y-MUX is coupled to one or more column decode lines and selectively couples a plurality of the sense amplifiers to a bus in response to an output of column address decoder coupled via the column decode lines.